Complimentary metal-oxide-silicon (CMOS) technology is used in many integrated circuits. CMOS technology utilizes n-channel metal-oxide-silicon field effect transistors (n-MOSFETs) often shortened to NFETs and p-channel metal-oxide-silicon field effect transistors (p-MOSFETs) often shortened to PFETs. Conventional NFETs and PFETs are well known in the art and comprise a source region and a drain region on opposite sides of a channel region formed in single-crystal silicon with a gate electrode formed on top of a gate dielectric layer which is itself formed on top of the channel region.
When NFETs and PFETs are used in high performance circuits, the PFETs need to be larger than the NFETs to overcome the difference in carrier mobility between NFETs and PFETs so as not to let the PFETs limit overall circuit switching speed. The hole mobility in PFETs is about 25% that of the electron mobility of NFETs. Larger PFETs require more silicon area and more power in a time when modern integrated circuits need to be smaller and consume less power in very many applications.
Therefore there is a need for both an improved PFET with high switching speed at reduced silicon area and power consumption compared to conventional PFETs and an NFET that may be fabricated simultaneously with the improved PFET.